Browse Prior Art Database

Method of Reading External Interrupts Into a VLSI Chip With Limited I/O Pins

IP.com Disclosure Number: IPCOM000036675D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Johnson, LE: AUTHOR

Abstract

External Interrupts are read into a VLSI chip interrupt subsystem using a small number of I/O pins, but without sacrificing interrupt latency or system interface bandwidth.

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Method of Reading External Interrupts Into a VLSI Chip With Limited I/O Pins

External Interrupts are read into a VLSI chip interrupt subsystem using a small number of I/O pins, but without sacrificing interrupt latency or system interface bandwidth.

The implementation described here uses 6 pins: 2 as an address for an external 4-to-1 4-bit multiplexer (MUX), and 4 to receive the multiplexer output signals.

The multiplexer address pins are driven by a 2-bit counter, cycled by the internal clock of the VLSI chip. The multiplexer inputs are taken from the interrupt signals.

Fig. 1 shows the logical connection used to implement the 4-bit read of the 16 interrupt lines.

(Image Omitted)

The 2-bit counter is driven by the VLSI clock, and provides an address for both the internal and external multiplexers. In the VLSI implementation, the internal multiplexer is imbedded in the same custom macro with the 16-bit register, forming a 16-bit 4-port register.

The input nibble is interleaved with the 16-bit register outputs in a fashion that causes 4 new interrupt bits to be stored in the register in the proper order, along with the 12 previously stored bits. Fig. 2 shows the interleaving scheme more clearly.

The interrupt controller internal to the VLSI chip is closely coupled to the chips' system interface, so that in an environment with multiple simultaneous interrupt requests, the processed interrupts can be transmitted across the system bus as quickly as allowed in the sys...