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Browse Prior Art Database

Data Security Through Dynamic Buffer Clearing

IP.com Disclosure Number: IPCOM000036677D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+2]

Abstract

Problem definition: An I/O Channel Controller (IOCC) implementation contains buffers which hold data during transfers between the system bus and system memory. The I/O architecture allows multiple first party DMA masters on the I/O bus to access these shared IOCC buffers. This means that two first party masters can use the same IOCC buffer when transferring data. However, one of these two masters must not be allowed to access data belonging to the other, or data security is compromised. There are many ways to provide data access security, but most of the obvious and classical approaches require either increased latency in the data transfers or more complex control hardware.

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Data Security Through Dynamic Buffer Clearing

Problem definition: An I/O Channel Controller (IOCC) implementation contains buffers which hold data during transfers between the system bus and system memory. The I/O architecture allows multiple first party DMA masters on the I/O bus to access these shared IOCC buffers. This means that two first party masters can use the same IOCC buffer when transferring data. However, one of these two masters must not be allowed to access data belonging to the other, or data security is compromised. There are many ways to provide data access security, but most of the obvious and classical approaches require either increased latency in the data transfers or more complex control hardware.

A simple and novel approach has been developed and implemented in the IOCC to provide data access security without impacting data transfer performance.

The IOCC data buffer implementation uses multi-port register files. When a buffer word is written to system memory using the register file's read port, the write port is written with zeros using the read address of the previous cycle.

Overlapping the read and write cycles in this manner solves the access security problem while maintaining minimum data transfer latency.

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