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Architecture for Interfacing a High Performance System Bus to a VLSI I/O Channel Controller

IP.com Disclosure Number: IPCOM000036679D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Johnson, LE: AUTHOR

Abstract

Disclosed is an efficient VLSI partitioning of state machine controllers and data-flow to communicate with a fast system bus.

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Architecture for Interfacing a High Performance System Bus to a VLSI I/O Channel Controller

Disclosed is an efficient VLSI partitioning of state machine controllers and data-flow to communicate with a fast system bus.

The Bus Interface Unit (BIU) includes a receive subsystem, a transmit subsystem, and an interrupt subsystem. The division of the BIU tasks into separate partitions allows overlapped sequencing of some initialization and handshaking cycles. The partitioning also simplifies individual state machine implementations.

The receive subsystem, indicated as (1) in the figure, is dedicated to detecting and initializing the I/O Channel Controller (IOCC) processing for PIO operations. It includes the following parts: Receive Handler: a finite state machine that

handles all Programmed Input/Output (PIO) Store

sequencing for the BIU, and initiates PIO Load

sequencing.

Error & Lock/Busy Handler: a finite state machine,

base- bounds address range comparator, and segment

register bit- field decoder that detect errors and

notify both the system processor and the IOCC

internal status handlers for error logging.

Cycle Counter: a counter that is loaded and

incremented by the receive handler to allow the

receive subsystem to synchronize with the

variable-length system bus cycles. The counter

provides end-of-transfer and overflow signals to

the receive handler.

Store Address Counter: provides addresses to the

internal IOCC data buffers.

The transmit subsystem (2) detects and processes requests for transmission of PIO load data, DMA address and data, and interrupt data to the system bus. The transmit subsystem consists of the following: Transmit Handler: a finite state machine that

provides overall control sequencing for bus

transmit operations.

Master Status Register & Bus Request Arbitration

section: detects and synchronizes bus transmit

requests, and starts the transmit handler; stores

status information for each transmit operation,

signals status to the IOCC; generates the system

bus control byte.

Ack Checker: a logic subsystem that ch...