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Additional Switching Regulator Loop for Large Step Load Changes

IP.com Disclosure Number: IPCOM000036692D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 27K

Publishing Venue

IBM

Related People

Hitchcock, LJ: AUTHOR [+3]

Abstract

A conventional switching power supply with a logic load is shown in Fig. 1. A duty cycle controlled transistor switch 10 modulates the supply voltage 12. The controlled voltage available at the secondary 14 of the power transformer 16 is smoothed by a low-pass filter comprising inductor L1 and capacitor C1. The output voltage Vout is held (Image Omitted) to the desired value Eref by the action of the control loop. A comparator 18 compares output voltage Vout to reference voltage Eref. The error voltage is used to produce the desired duty cycle from modulator 20. Comparator 18 uses the error voltage from the error amplifier 22 as well as the switch current and compares the two signals to control the time for which the transistor switch 10 is on.

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Additional Switching Regulator Loop for Large Step Load Changes

A conventional switching power supply with a logic load is shown in Fig. 1. A duty cycle controlled transistor switch 10 modulates the supply voltage 12. The controlled voltage available at the secondary 14 of the power transformer 16 is smoothed by a low-pass filter comprising inductor L1 and capacitor C1. The output voltage Vout is held

(Image Omitted)

to the desired value Eref by the action of the control loop. A comparator 18 compares output voltage Vout to reference voltage Eref. The error voltage is used to produce the desired duty cycle from modulator 20. Comparator 18 uses the error voltage from the error amplifier 22 as well as the switch current and compares the two signals to control the time for which the transistor switch 10 is on.

In circuits that incorporate CMOS logic, when the logic is turned ON or OFF, the load current demanded of the power supply changes appreciably __ sometimes by as much as 70% in a few microseconds. Under these conditions the output voltage tends to exceed the regulation boundary, causing logic malfunction.

A separate circuit for improving output voltage regulation under high-step load conditions is herein disclosed (Fig. 3). Referring also to the timing diagram (Fig. 2), the circuit senses the output voltage which changes with the load current. For an increase in load, such as would be caused by logic turning ON, the output voltage starts to decrease. The circuit rapidly senses this sharp decrease and overrides the error voltage in such a way as to increase the duty cycle to its maximum value in one switching cycle. The increase in d...