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Method for Simulating a Latch-Trigger Logic Design

IP.com Disclosure Number: IPCOM000036694D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Buonomo, JM: AUTHOR

Abstract

A typical implementation of a latch-trigger logic circuit requires two latches (L1 and L2) for each SRL in the circuit. Two non-overlapping clocks (C1 and C2) are required throughout the device to clock the pairs of latches, as shown in Fig. 1.

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Method for Simulating a Latch-Trigger Logic Design

A typical implementation of a latch-trigger logic circuit requires two latches (L1 and L2) for each SRL in the circuit. Two non-overlapping clocks (C1 and C2) are required throughout the device to clock the pairs of latches, as shown in Fig.
1.

In a zero delay logic simulation, each SRL can be modeled as a single latch (L1) which is controlled by a single clock (C1), as shown in Fig. 2. The clock must be shortened in duration to less than the latch set-up time. This maintains the integrity of the logical state of the design.

The resulting model is significantly smaller due to the decreased gate count. Performance is improved, also, because simulation events occur only once per cycle instead of twice. This method improves simulation performance and eases capacity limitations on both hardware and software simulators.

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