Browse Prior Art Database

Comparator Set/Reset Latch

IP.com Disclosure Number: IPCOM000036696D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Trudgen, GA: AUTHOR

Abstract

A set/reset latch, configured from analog building blocks (comparators), is disclosed (Fig. 1). Since this circuit is compatible with logic signal levels, it can be interfaced directly to logic signal control.

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Comparator Set/Reset Latch

A set/reset latch, configured from analog building blocks (comparators), is disclosed (Fig. 1). Since this circuit is compatible with logic signal levels, it can be interfaced directly to logic signal control.

Input lines (SET and RESET) are driven from unloaded sources (not shown). The circuit functions identically to a set/reset latch configured from logic blocks, as shown in the timing diagram (Fig. 2). The latch is set when the SET input goes negative. The output goes to its up level and remains there until a -RESET signal occurs. A logic signal threshold is established by resistor divider R1 and R2.

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