Browse Prior Art Database

Enabled Flip-Flop for Frequency Division

IP.com Disclosure Number: IPCOM000036700D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Strayer, DE: AUTHOR

Abstract

The disclosed circuit produces an output clock having the same frequency as an input clock or some sub-octave or fractional frequency of the input. Conventionally, a number of toggle flip-flops are chained together, and a multiplexer chooses among their outputs. Each tap further down the chain, however, is delayed by its trip through an additional flip-flop, and flip-flops at the end of the chain are always running. Moreover, noise from the slower-running flip-flops can affect the multiplexer, causing undesirable edge jitter on the output.

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Enabled Flip-Flop for Frequency Division

The disclosed circuit produces an output clock having the same frequency as an input clock or some sub-octave or fractional frequency of the input. Conventionally, a number of toggle flip-flops are chained together, and a multiplexer chooses among their outputs. Each tap further down the chain, however, is delayed by its trip through an additional flip-flop, and flip-flops at the end of the chain are always running. Moreover, noise from the slower-running flip-flops can affect the multiplexer, causing undesirable edge jitter on the output.

The present circuit is an augmented flip-flop that either toggles like a normal flip-flop or passes its clock to its output, depending on the state of its "enable" input. A series of these augmented flip- flops (Fig. 1) is chained together to provide the desired frequency- selection function. The change in delay, when one circuit goes from passing the clock to dividing the clock in half, is less than the delay through a flip-flop. No part of the circuit runs slower than the output; so no low-frequency noise is generated.

A schematic diagram of the circuit is shown in Fig. 2. When the flip-flop is enabled (+EN is at a higher voltage than -EN), current is supplied to a standard master-slave flip-flop circuit (Q1 through Q12). When the flip-flop is disabled, current is removed from Q1 - Q12 and is applied instead to Q13 and Q14, which pass the input clock directly to the output.

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