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Integrated Store Immediate Operations

IP.com Disclosure Number: IPCOM000036707D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Ngai, CH: AUTHOR [+2]

Abstract

When an instruction processing unit (IPU) is executing a 370 instruction of integrated store immediate operation (SI-OPS), for example, AND Immediate (AI), OR Immediate (OI), and Exclusive OR Immediate (EOI), where one operand is included in the instruction (i.e., immediate) and the other is obtained from storage (in this case a fast read/ write (RD/WR) buffer or cache), it would originally take three microwords or up to 14 clock pulses to complete the operation. The sequence of events would be as follows: 1. A RD micro-word is issued to obtain the second operand from storage. 2. A one-byte logical micro-word is then issued which includes the first operand to perform the indicated operation. The Op-code will indicate the operation to take place.

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Integrated Store Immediate Operations

When an instruction processing unit (IPU) is executing a 370 instruction of integrated store immediate operation (SI-OPS), for example, AND Immediate (AI), OR Immediate (OI), and Exclusive OR Immediate (EOI), where one operand is included in the instruction
(i.e., immediate) and the other is obtained from storage (in this case a fast read/ write (RD/WR) buffer or cache), it would originally take three microwords or up to 14 clock pulses to complete the operation. The sequence of events would be as follows:
1. A RD micro-word is issued to obtain the second operand

from storage.
2. A one-byte logical micro-word is then issued which

includes the first operand to perform the indicated

operation. The Op-code will indicate the operation to

take place. The condition code based on the result is

also obtained at this time.
3. Finally a WR micro-word is issued to store the result

back into the same storage location that the second

operand was fetched from.

(Image Omitted)

In terms of clock cycles the operation would appear as shown in Fig. 1.

An improvement is achieved when all three micro-words are integrated into one thereby reducing the clock pulses required from 14 to 6, by creating new micro-word commands for the three SI-opcodes of the 370 instructions and enhancing cache operation by adding a one- byte logical unit.

The cache with its own 8-bit logic unit is now capable of performing any of the three previously mentioned operati...