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Synchronizing Storage Request Buffer

IP.com Disclosure Number: IPCOM000036713D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 15K

Publishing Venue

IBM

Related People

Bishop, JW: AUTHOR [+4]

Abstract

In a particular system the implementation of a synchronizing mechanism between asynchronous storage and channel subsystems is accomplished using multiple buffers and single points of metastability removal. The configuration is referred to as a synchronizing storage request buffer (SSRB) and works as described in the following:

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Synchronizing Storage Request Buffer

In a particular system the implementation of a synchronizing mechanism between asynchronous storage and channel subsystems is accomplished using multiple buffers and single points of metastability removal. The configuration is referred to as a synchronizing storage request buffer (SSRB) and works as described in the following:

The SSRB allows each subsystem to run at its own independent clock rate. The SSRB hardware can be packaged with either subsystem but should be packaged with the subsystem having the faster clock rate so that data sent between the subsystems will be sent at the slower clock rate. Sending data at the slower clock rate allows longer cables to be used between the subsystems.

Many advantages arise because both subsystems can be designed to accommodate independent cycle times. Each subsystem can be designed for the cycle time that is most efficient and practical for its hardware. Each subsystem can be designed with different technologies as long as the technology is compatible with that of the SSRB. For upgrades, one subsystem could redesign to a faster cycle time without any changes required in the other subsystem. The channel subsystem could be attached to any machine that supported the SSRB.

The main concern of synchronizing signals between clocks running at different rates is the problem of metastability. Metastability occurs when the signal to the data port of a latch is changing (not a defined '0' or '1' logic level) when the clock is going away. The output of the latch may go to a metastable state, whose characteristics depend on the technology, before settling to a stable, defined logic level. Metastability can be controlled by allowing enough time for the possible metastable conditions to become stable.

The metastable time is encountered twice per each channel request. Although the service time for a single request is increased due to the metastable time, using multiple buffers can hide the metastability time by overlapping it with useful work. While one request is being processed, metastability can be removed from the other requests. Processing of another request can then start immediately when the present request is completed. This synchronizing would not be practical for the instruction processing unit (IPU) because the metastability time would have a direct impact on performance. The I/O subsystem can tolerate this time because a single channel does not require the full capacity of storage. Because each channel executing a channel command word (CCW) string is an independent process, the channel subsystem has an ideal a situation for pipelining, and can thus provide multiple requests to storage.

Three selected buffers will hold the command, address, access key, status and data of each channel request. The buffers are necessary to maintain the needed bandwidth across the data bus between the channel and storage subsystems. The buffers provide an efficient conversion...