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Algorithm to Automatically Determine the Optimum Methodology for Processing Logic Circuits

IP.com Disclosure Number: IPCOM000036719D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 31K

Publishing Venue

IBM

Related People

Shearon, PC: AUTHOR

Abstract

An algorithm, implemented in the test generator ETG, automatically determines the optimum methodology (in terms of test coverage, run time, and test patterns) for processing logic circuits. It does this based on information available from the user, information available about the logic circuit, and the test generation capabilities available in ETG. The three basic types of information it works with are the user and part characteristics (METHCODE), the various modes of test generation capabilities (MODECODE), and the various approaches to test generation on objectives (OBJCODE). Each type of information is described in the following: METHCODE is shown as follows: C5 C4 C3 C2 C1 Where: METHCODE MEANING '10'X C5=1: Multiple input changes required.

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Algorithm to Automatically Determine the Optimum Methodology for Processing Logic Circuits

An algorithm, implemented in the test generator ETG, automatically determines the optimum methodology (in terms of test coverage, run time, and test patterns) for processing logic circuits.

It does this based on information available from the user, information available about the logic circuit, and the test generation capabilities available in ETG. The three basic types of information it works with are the user and part characteristics (METHCODE), the various modes of test generation capabilities (MODECODE), and the various approaches to test generation on objectives (OBJCODE). Each type of information is described in the following:
METHCODE is shown as follows: C5 C4 C3 C2 C1

Where:

METHCODE

MEANING '10'X C5=1: Multiple input changes required. '08'X C4=1: The logic circuit contains a shift register latch (SRL). '04'X C3=1 The logic circuit contains an array. '02'X C2=1: The logic circuit contains CMOS logic. '01'X C1=1: The logic circuit follows the LSI design constraints.

MODECODE is shown as follows:

M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 Where:
MODECODE
MEANING '800'X M12=1: Imply the line-hold and tie net values. '400'X M11=1: Imply all net values. '200'X M10=1: Create LSSD patterns for arrays. '100'X M9 =1: Prevent any glitch on the array write line. '080'X M8 =1: Assign the X value address lines to all 0's or all 1's only. '040'X M7 =1: Allow the use of the scan input o...