Browse Prior Art Database

Matrix Display Using Electron-Emission Devices

IP.com Disclosure Number: IPCOM000036727D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Cronin, JE: AUTHOR [+3]

Abstract

Microelectronic device processing steps are selectively combined to make a flat plate display comprised of an array of field-emission devices individually switchable to excite selected phosphor dots.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 62% of the total text.

Page 1 of 2

Matrix Display Using Electron-Emission Devices

Microelectronic device processing steps are selectively combined to make a flat plate display comprised of an array of field-emission devices individually switchable to excite selected phosphor dots.

Referring to Fig. 1, insulating substrate 12 is coated with a conductor 14 and patterned, if required. Boron-phosphorous-silicon glass (BPSG) 16 and spun-on glass 18 are applied and reflowed to form a smooth surface. An image comprised of an array of circles is then photo-processed and etched through layers 18 and 16, stopping on conductor 14. A conformal layer of parylene is then deposited, followed by anisotropic etching to leave sidewall coatings 20. Dilute hydrofluoric acid is used to etch away the more porous glass 18 without seriously attacking denser glass 16 and not attacking parylene sidewall coatings 20 at all.

Referring to Fig. 2, tungsten 22 is deposited and planarized. Then, parylene 20 is etched back and sputter etching is used to shape tungsten 22 to a sharp tip in emitter regions 22E while edges are beveled in control grid regions 22G. Parylene (not shown) is added and planarized to provide a flat surface and protection of emitter tips during the next etching process. Tungsten 22G is patterned and etched to create control grid lines parallel to the plane of the figure which are slightly wider than emitter tip hole diameter d to assure control grid line continuity.

Referring to Fig. 3, insulator layer 24 i...