Browse Prior Art Database

Data Latch for a Single-Ended Data Line

IP.com Disclosure Number: IPCOM000036731D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Andoh, H: AUTHOR [+3]

Abstract

To permit sensing a signal having a voltage level lower than a threshold voltage (Vt) on a single-ended data line, a master-slave data latch circuit is designed to decouple a large data line load from the latching operation.

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Data Latch for a Single-Ended Data Line

To permit sensing a signal having a voltage level lower than a threshold voltage (Vt) on a single-ended data line, a master-slave data latch circuit is designed to decouple a large data line load from the latching operation.

Referring to the figure, transistors T3 and T4 of the master latch are mismatched in length to favor setting data line 2 in a high state. Current levels through T3 and T4 are set to provide sufficient signal margin. While the data line 2 and line 4 are not equally loaded, capacitive device C1 compensates for transistor T1 being larger than T2 to make nodes N1 and N2 equally loaded. True and complement signals that feed to the rest of the data path originate at nodes N1 and N2. Nodes N1, N2, N3, N4, and N5 are all precharged from the same point on the voltage supply Vdd network to avoid voltage supply variation effects on the signal level.

At the beginning of a cycle, inputs 10 and 12 start low. Input 10 charges data line 2, and nodes N1, N2, N3, N4, and N5 to supply voltage Vdd through transistors T10, T13, T14, T15, T16, and T17. Just before signal development, input 10 goes high, thereby shutting off precharge transistors T10, T15, T16, and T17. Signal develops for a predetermined time and is then passed to the master latch through transistors T13 and T14. Input 12 then goes high which starts a slow set of node N3 through small transistor T5 to enhance the signal. Transistor T5 is designed to bring no...