Browse Prior Art Database

Trench PLANARIZATION and Simultaneous Formation of Buried Contact for High-Density DRAM Cells

IP.com Disclosure Number: IPCOM000036743D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 133K

Publishing Venue

IBM

Related People

Arienzo, M: AUTHOR [+5]

Abstract

A technique is described whereby trench planarization and buried contact are simultaneously fabricated, for high density DRAM cells, through a series of unique processing steps. Two methods are described to produce a DRAM cell with a buried contact between source and trench-storage node, using selective epitaxial growth techniques during trench planarization. (Image Omitted)

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 4

Trench PLANARIZATION and Simultaneous Formation of Buried Contact for High-Density DRAM Cells

A technique is described whereby trench planarization and buried contact are simultaneously fabricated, for high density DRAM cells, through a series of unique processing steps. Two methods are described to produce a DRAM cell with a buried contact between source and trench-storage node, using selective epitaxial growth techniques during trench planarization.

(Image Omitted)

Typically, a DRAM cell with a trench capacitor requires a solid contact between the trench-storage node and the source region. A polysilicon contact generally requires two additional masks. The use of a salicide (TiSi2) bridge is only feasible when the trench surface is almost perfectly planarized with the substrate surface. This is considered difficult to achieve, since reactive ion etching (RIE) steps following trench planarization may change altitudes of surfaces with different material and dopant concentrations, even if the surface is perfectly uniform at the beginning. Also, a vertical buried contact inside the trench requires critical control of the photoresist planarization.

The methods described herein enable trench planarization and buried contact to be attained simultaneously. The two processing methods described are: 1) the use of RIE planarization and 2) the use of chemical-mechanical polishing techniques. The key features are: a) the use of one mask for the buried contact sites; b) filling the trenches with thick polysilicon after trench RIE; and c) planarizing the trenches and forming a buried contact with selective epitaxial growth.

Note that recessed oxide (ROX) is used for isolation so that a thick oxide can remain under the adjacent wordline, as shown in the

(Image Omitted)

final DRAM structure (Fig. 1). The trench is designed such that boron concentration out-diffusing from the buried contact is restricted within the trench definition. At the same time, the contact between the source and the storage section is secured, as illustrated in the circuit layout of Fig. 2.

The processing steps for the two methods are as follows:

RIE PLANARIZATION METHOD:

1) Use p-epi/P+-substrate. Define N-well and grow

oxide.

2) Deposit nitride/polysilicon.

3) Lithography for buried contact, etch

polysilicon/nitride, as shown in Fig. 3.

4) Deposit CVD oxide, as shown in Fig. 4.

5) Lithography for trench, etch...