Browse Prior Art Database

Gate-Array Cell to Improve Circuit Density on Chip

IP.com Disclosure Number: IPCOM000036744D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Blachere, JM: AUTHOR [+3]

Abstract

This article describes a new gate-array cell which improves circuit density on chip, while enhancing global wiring capability.

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Gate-Array Cell to Improve Circuit Density on Chip

This article describes a new gate-array cell which improves circuit density on chip, while enhancing global wiring capability.

The current gate-array basic cell shows a common size for each transistor. The major drawback of this kind of cell is the design of the latches. Latches built with constant-size transistors need complex schematics, in order to perform their function. To design a simple polarity hold SRL, almost 34 transistors are needed, as well as 11 internal wiring channels, to connect all these transistors. This is due to the fact that no difference in transistor size could be found in such a gate-array cell. A complex latch schematic, involving true and inverting clocks to control the inverter loops, and the feedback as well, has to be used. So each clock will need a supplementary inverter, and each inverter loop (master and slave) will need two double transfer-gates.

A new gate-array cell, as shown in the figure, is proposed in order to simplify latch schematics and thus reduce their personalization and wiring channels needed for internal wiring (circuit design). The freed wiring tracks could be used as global wiring tracks in order to connect circuits together and to improve on- chip circuit density.

This new gate-array cell shows a short transistor, which is used in latch core. For random logic circuits, this short transistor is turned-off for device isolation purposes.

With this new cell, inverted...