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Bi-Cmos LSSD Latch in Integrated Complementary Logic

IP.com Disclosure Number: IPCOM000036747D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+3]

Abstract

The present Bi-CMOS latch proposal is based on the use of complementary NPN and PNP transistors in emitter follower mode driven by a CMOS logic circuit. This Bi-CMOS polarity hold latch follows the LSSD (Level Scan Sensitive Design) concept. This new latch circuit is an L1 latch (Master) and can be extended to an L1/L2 (Master/Slave) latch in the same way. The major interest of this type of circuit is its density and speed compared to conventional CMOS latches.

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Bi-Cmos LSSD Latch in Integrated Complementary Logic

The present Bi-CMOS latch proposal is based on the use of complementary NPN and PNP transistors in emitter follower mode driven by a CMOS logic circuit. This Bi-CMOS polarity hold latch follows the LSSD (Level Scan Sensitive Design) concept. This new latch circuit is an L1 latch (Master) and can be extended to an L1/L2 (Master/Slave) latch in the same way. The major interest of this type of circuit is its density and speed compared to conventional CMOS latches.

The +L1/-L1 ICL latch comprises a storage cell having two small FETs (PUP and NDN) driven by the -L1 output. The -L1 output signal is generated from the +L1 signal through the ICL Inverter2. A Bi-CMOS ICL inverter (Inverter1) generates the C Clock complementary signal. The logic part of the latch is built with a mix of two boolean functions, i.e., a 2-way NOR and NAND. The 2-way NOR function comprises two PFETs P1 and P2. The two inputs are the complementary C Clock and the Data input. This NOR2 function provides L1=1 (L1=0) when Data=0. The 2-way NAND function comprises the two NFETs N1 and N2. The two inputs are the C Clock and the Data input. The NAND2 function provides L1=0 when Data=1.

One inverter circuit (Inverter2), built with the integrated complementary logic (ICL) concept, is necessary to generate -L1 from +L1. The other ICL inverter (Inverter1), useful to generate the C Clock, drives many other ICL Latches (e.g.,
30).

READ Mode: The small PFETs/NFETs (...