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Browse Prior Art Database

RAM Control Mechanism for Simultaneous RAM Accesses

IP.com Disclosure Number: IPCOM000036749D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 92K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

This article describes a circuit arrangement to control and allow two asynchronous sources to access a random-access memory (RAM) along with one synchronous source.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

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RAM Control Mechanism for Simultaneous RAM Accesses

This article describes a circuit arrangement to control and allow two asynchronous sources to access a random-access memory (RAM) along with one synchronous source.

The circuit arrangement disclosed herein provides a means of loading or reloading a RAM from three distinct sources. Two sources are asynchronous and must be brought in sync with the RAM clock, and all three sources of request must be handled with a priority given to each source.

In a system controlled by level sensitive scan design (LSSD) clocks, a machine cycle may be defined as shown in Fig. 1 which illustrates typical LSSD clocks. A RAM clock is created from the LSSD clocks so that two RAM accesses may occur each cycle, thus allowing multiple sources to access the RAM each cycle.

(Image Omitted)

The three sources of data are as follows:

1. Microprocessor (MP) read/write data requests.

2. Packet data sent or received each cycle for up to

35 cycles.

3. Data loaded into or read from an external memory

where each data access will occur every N cycles,

with N determined by the speed of the external

memory. N may be 1, 2, 3, 4, etc. and up to 32

transfers may occur.

A circuit diagram of the microprocessor RAM access is shown in Fig. 2. The MP may access the RAM by issuing either of two read or write instructions depending upon which area of the RAM is to be accessed. If a RAM read instruction is issued, then a sense strobe will accompany it, and if a write instruction is issued, a control strobe will be issued. The strobes occur when all bits of the instruction address (and data) are stable and they are asynchronous to the RAM clocks. MP RAM accesses have the highest priority and inhibit all other RAM requests.

When the strobes are received, shift register latches (SRLs) 1A and/or 1B will be set along with SRL 2B if a write to RAM is required. Due to variations in signal delay, it is possible that more than one latch should be set, but only one is actually set; this is covered by the design since the remaining SRLs to be set will be set at the same time SRL 2A is set to begin the RAM cycle.

(Image Omitted)

SRL 2A gates the MP address to RAM. If a write RAM is to be performed, SRL 2A also gates the data to RAM. When SRLs 2A and 2B are set, the + RAM clock signal causes write RAM high word and/or write RAM low word signals to become active and store the desired data. SRL 2A also turns on SRL 3. Due to the varying characteristics of the MPs used, the strobes may be present for a

1

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considerable time after the MP RAM cycle is completed and SRL 3 inhibits a second unwanted MP RAM cycle from occurring. When SRL 3 is active and all strobes are inactive, the SRLs shown in Fig. 2 are reset to their inactive state. A circuit diagram of the packet RAM access is shown in Fig. 3. For the asynchronous external pa...