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ECL to Bi-Cmos Level Converter With ECL Amplifier

IP.com Disclosure Number: IPCOM000036753D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 102K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+3]

Abstract

With VLSI improvements, the density of circuit per chip increases, but this integration is limited by the power dissipation allowed by the packaging in the case of an ECL (emitter-coupled logic) type of circuit. This article describes an interface circuit which permits merging on the same chip islands of logic with ECL circuits (low swing signal) with islands of Bi-CMOS circuits. Prior art reports the use of PFETs connected in a differential pair to perform the shifting and the amplification of the ECL signal. This kind of circuit suffers from the relative poor performance of the PFETs which are usually slow circuits (input ECL voltage swing and threshold voltage sensitivity).

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ECL to Bi-Cmos Level Converter With ECL Amplifier

With VLSI improvements, the density of circuit per chip increases, but this integration is limited by the power dissipation allowed by the packaging in the case of an ECL (emitter-coupled logic) type of circuit. This article describes an interface circuit which permits merging on the same chip islands of logic with ECL circuits (low swing signal) with islands of Bi-CMOS circuits. Prior art reports the use of PFETs connected in a differential pair to perform the shifting and the amplification of the ECL signal. This kind of circuit suffers from the relative poor performance of the PFETs which are usually slow circuits (input ECL voltage swing and threshold voltage sensitivity).

This novel ECL to Bi-CMOS level converter with ECL amplifier circuit allows a very high speed level conversion compared to existing circuits. The circuit which interfaces the ECL circuit with the Bi- CMOS circuit is shown in the figure. This circuit is based on a 2 VBE level shifter followed by a current switch (ECL amplifier) terminated in an emitter follower to give Bi-CMOS levels compatibility.

The basic circuit is composed of two symmetrical shifters which lower the ECL level by 2 VBEs. The shifted signals are then amplified in the ECL circuit which comprises NPN transistors T1, T2, T3 and T4 and resistors R1, R2 and R3. Due to the fact that the current in R3 is the same as in R1 or R2, the lower level of the signal has a low variation when the temperature or power supply varies. This permits having a lower level on node A and B (NPN collector of T1 and T2) without a problem of saturation of the transistors which could result in a lower speed. The saturation of transistors in the current switch is avoided by using a current m...