Browse Prior Art Database

Multiple Microprocessor Interfaces for a General-Purpose Control Module

IP.com Disclosure Number: IPCOM000036757D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 118K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

This article describes a method of designing a general-purpose control/ interface module to operate properly with a plurality of microprocessors.

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Multiple Microprocessor Interfaces for a General-Purpose Control Module

This article describes a method of designing a general-purpose control/ interface module to operate properly with a plurality of microprocessors.

In the method disclosed herein, step 1 is to define a group of

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"N" jumper pins or latches set at power-on time. These jumpers/latches are then decoded to identify the microprocessor that is desired to be connected to the general purpose control interface module. A typical microprocessor jumper decode listing is shown in table 1 (Fig. 1).

Step 2 is to design general-purpose sequences that can be readily adapted to any microprocessor instead of designing a custom sequence for each microprocessor. For example, consider when the general-purpose control/interface module needs to take a bus cycle (cycle steal). The general timing sequence may be designed as shown in Fig. 2.

From the timing chart it can be seen that by "ANDing" or "ORing" the proper phases of the various sequence latches, various length signals occurring at any clock interval may be easily formed. Some signals are those that gate the address and data onto the bus, read/ write signals, strobes, etc. With this methodology it is almost always possible to meet the specifications of the selected microprocessor type and its bus controller.

Step 3 in designing a multiple micro-interface is to look at the control, address, and data interface pins required in each microprocessor int...