Browse Prior Art Database

Simplified Ic Fabrication Through Laser Planarization

IP.com Disclosure Number: IPCOM000036758D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Andreshak, JC: AUTHOR [+3]

Abstract

Disclosed is a process for fabricating multi(metal)layer integrated circuit interconnect structures employing pulsed laser melting of the metal layers therein.

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Simplified Ic Fabrication Through Laser Planarization

Disclosed is a process for fabricating multi(metal)layer integrated circuit interconnect structures employing pulsed laser melting of the metal layers therein.

Following the fabrication of inter(metal)layer vias or contacts to underlying silicon in insulating layers (Fig, 1), a metal layer is deposited by a relatively simple technique, e.g., sputtering (Fig. 2). Subsequently, the metal layer is melted by irradiating the metal layer with laser pulses of sufficient intensity, wavelength and duration to allow the metal to flow into and completely fill vias and form a planar top surface (Fig 3). The planar metal layer so formed on top of the insulating layer can then be patterned to form the overlaying circuitization layer (Fig. 4).

The fabrication sequence, described above, can be repeated to fabricate an arbitrary number of layers in an interconnect structure.

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