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Phase Error Detect Logic for Disk File Speed Control

IP.com Disclosure Number: IPCOM000036762D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Elliott, PJ: AUTHOR [+3]

Abstract

A phase error detect circuit is described for controlling the speed of a disk file spindle motor. The scheme makes use of the pulses from the servo disk and bit pulses from a crystal oscillator to decrement respective counters which are initially loaded with the counter corresponding to the sampling period. The contents of the bit decrement counter represent a virtually continuous measurement of phase error which may be sampled and held in a bit error register, as required. The advantages of the system are that there is no arithmetic addition required, thus reducing the size of logic; also, there is a programmable sample time allowing the bandwidth of response to be controlled by software.

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Phase Error Detect Logic for Disk File Speed Control

A phase error detect circuit is described for controlling the speed of a disk file spindle motor. The scheme makes use of the pulses from the servo disk and bit pulses from a crystal oscillator to decrement respective counters which are initially loaded with the counter corresponding to the sampling period. The contents of the bit decrement counter represent a virtually continuous measurement of phase error which may be sampled and held in a bit error register, as required. The advantages of the system are that there is no arithmetic addition required, thus reducing the size of logic; also, there is a programmable sample time allowing the bandwidth of response to be controlled by software.

The spindle motor in Fig. 1 is a three-phase eight-pole brushless DC motor with electronic commutation. Commutation sensors determine the position of the rotor, and the commutation logic generates six logic lines that are used by the motor driver.

The demodulated output from the servo disk 1 is measured against the crystal oscillator by the phase error detection logic, and an eight-bit phase error signal is produced. This is read by the digital signal processor (DSP) which contains a position control algorithm. The DSP output is an eight-bit word 2 for conversion to a pulse-width

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modulated (PWM) control signal by the PWM generation circuit.

The PWM 3 signal is then combined with the motor drive signals in the commutation logic.

Servo Identification Signals (SIDs) 4 from the servo disk provide position information. The phase error logic is shown in Fig. 2. The DSP writes a 16-bit word to the two input registers 5 and 6. the most significant 8 bits (MSB) represent the number of SID pulses that will define a sample period for phase measurement. The least significant 8 bits (LSB) contain the remainder that would be left in the bit decrement counter if the disk velocity remained constant and correct throughout the sample period (i.e., the 8 LSBs of the number of cycles of the oscillator in the sample period). At the start of the sample, the SID decrement counter is loaded from the SID register and the bit decrement counter is loaded from the bit count register.

The bit decrement counter is clocked at a constant rate by the oscillator and is allowed to wrap around. The counter continually decrements, as long as oscillator pulses are present. Meanwhile, the SID decrement counter is decremented by incoming SID pulses from the DEMOD logic until it reaches zero, and the current value of the bit decrement counter is loaded into the bit error register SID to represent the phase error signal 7. The SID decrement counter is reloaded from the SID count register as soon as it reaches zero....