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Repeating Microcode Words for Fast Controlled Repeat Cycle Functions

IP.com Disclosure Number: IPCOM000036793D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Concha, FF: AUTHOR [+2]

Abstract

This article describes a mechanism which provides a repeat cycle enabling function in a microprogram-controlled processor.

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Repeating Microcode Words for Fast Controlled Repeat Cycle Functions

This article describes a mechanism which provides a repeat cycle enabling function in a microprogram-controlled processor.

In microcode-controlled processors, repeating operations are usually performed in a microcode test and branch loop requiring an extra test and branch microcode word execution time for each time through the loop. The mechanism of this disclosure provides for elimination of the test and branch microcode word and the time for its execution.

Many functions performed by microcode-controlled processors require looping functions such as repeat addition cycles for multiplication, repeat shifting for divide alignment, repeat subtraction for divide and repeat shifting for floating- point normalization, convert hex to floating point, and floating-point equate exponents. The hardware provided in the processor illustrated in the drawing provides for the repeat execution of selected micro-control words during the previously mentioned operations.

As each of the looping micro-control words begins execution, a loop on the microword control latch is set at (a). This latch controls the gating of micro- control words into the control register at (b). If the latch is ON, the control word clocked into the control register at the beginning of the next cycle will be from the output of the current control register instead of control ROS. This pattern will continue for each cycle until the latch is r...