Browse Prior Art Database

High Speed Parallel Bus Arbitration

IP.com Disclosure Number: IPCOM000036796D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Chang, Y: AUTHOR [+2]

Abstract

This article describes a technique to handle contention on an I/O processor (IOP) to communicate data between multiple chips on the IOP internal bus.

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High Speed Parallel Bus Arbitration

This article describes a technique to handle contention on an I/O processor (IOP) to communicate data between multiple chips on the IOP internal bus.

The bus arbitration (BA) scheme disclosed herein manipulates multiple bus requests and grants one request at a time according to a predefined priority algorithm. The multiple chips include random- access memory (RAM) and Motorola 68020. Also included are chips SPB, IOB and IDLC which are names of chips in the bus system.

Fairness, fast response, preemptive capability and variable data length packet handling are solved by the bus arbitration (BA) of this disclosure. The circuit design of the BA unit is illustrated in block diagram in the drawing. The following three key set signals are defined to solve the problem:

1. BR: Six bus request (BR) lines are driven to the BA unit. Each chip can activate its own BR line to request the bus. The IOB chip can activate either BREQH or BREQ2 for fast or slow IO transfer, respectively.

2. BG: Five bus grant (BG) lines are driven from the BA unit to the chips. The BA can activate one BG one time to a specific bus master. Only one BG line is driven to the IOB chip to represent either fast or slow transfer.

3. Done: A bidirectional single line is shared by the BA unit and all other chips. The bus master activates this line to indicate the completion of the bus arbitration.

Ten units are included in the circuit design as follows:

1. A snapshot window captures all incoming bus requests for one cycle. Thereafter, the window closes and all subsequent requests are ignored until all requests in the window are serviced. For periods when there are no active bus requests, the window will remain open waiting for any request to become active. Whenever the bus request originator receives the bus grant from the bus arbitration unit, it should deactivate its BR and become the bus master.

2. BR shift register latches (SRLs) latch the BR signals when the snapshot window is open and hold BRs when the window is closed. They are reset by corresponding BG SRLs. IOBH is a special case which can set its own BR SRL even if the snapshot window is closed and will be described in IOBH bump logic.

3. Valid logic compares the external BR with the BR SRLs to validate the bus request. It voids the BR SRL if external BR is inactive.

4. Bypass logic accepts either from external BR directly as the snapshot window just opens or from the BR SRLs through the valid logic when the window is closed.

5. A priority multiplexer issues the BG according to the priority scheme. Only one BG can be issued at one time.

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6. BG OR logic accepts and ORs two sets of BG signals. The first BG signal is activated by the BR signal on the same cycle; the second BG signal is exactly the same BG but generated from the BG SRL on the followin...