Browse Prior Art Database

Interface Logic Control for a Fully Associative Table Lookup/Lookaside Buffer

IP.com Disclosure Number: IPCOM000036798D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Williams, T: AUTHOR

Abstract

A logic circuit implementation is described which creates a fully associative Table Lookup/Lookaside Buffer (TLB) consisting of 1) a content-addressable memory (CAM) array containing virtual address equivalents of the contents in cache memory and 2) a random-access memory (RAM) array containing the physical location in cache corres (Image Omitted) ponding to entries stored in the CAM. When there is a match between CAM word location and input data, the RAM location containing the physical cache address needed to fetch requested data is immediately and directly accessed.

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Interface Logic Control for a Fully Associative Table Lookup/Lookaside Buffer

A logic circuit implementation is described which creates a fully associative Table Lookup/Lookaside Buffer (TLB) consisting of 1) a content-addressable memory (CAM) array containing virtual address equivalents of the contents in cache memory and 2) a random-access memory (RAM) array containing the physical location in cache corres

(Image Omitted)

ponding to entries stored in the CAM. When there is a match between CAM word location and input data, the RAM location containing the physical cache address needed to fetch requested data is immediately and directly accessed.

Referring to Fig. 1, a typical configuration of Y, X bit words of virtual addresses resident in cache is stored in the CAM array. Corresponding Y, N bit words of physical addresses of cache data are stored in RAM. Bit words X and N may contain mask bits or other information and may vary in size.

Other features include clock control 2 having a read/write and clock inputs 4 providing output 6 to connecting logic 8 and a write decode 10, with address inputs 12.

Detail of connecting logic 8 is shown in Fig. 2. Clock input 6 allows synchronous TLB operation under microprocessor control and other inputs for read control 14 and CAM match line 16. Decoded outputs 18 and 20 select RAM and CAM word lines for write operations input 34 and provide direct CAM selection via input 16 of the RAM word lines 18 during match operations.

When activated by a positive active clock signal at 6, virtual address and mask bit data are passed by the input drivers into the CAM for comparison with stored data. The clock signal is delayed a time T before entering NAND circuit A. Time T is designed to allow CAM compariso...