Browse Prior Art Database

Software Control of HARDWARE With Write-Only Control Registers Shared Between Devices

IP.com Disclosure Number: IPCOM000036801D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 6 page(s) / 51K

Publishing Venue

IBM

Related People

Billingsley, RE: AUTHOR [+3]

Abstract

This article describes a method to handle write-only hardware control registers that are shared between devices and code entities.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 26% of the total text.

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Software Control of HARDWARE With Write-Only Control Registers Shared Between Devices

This article describes a method to handle write-only hardware control registers that are shared between devices and code entities.

In a communications system where a set of hardware registers is provided for control registers that are common to up to 4 ports and that would require access by interrupt level and task level logic of one or more tasks, several major problems can exist, such as each task (and interrupt routine) could write to the hardware at any time independently. The tasks do not run the same software set, and there is no mechanism to prevent an interrupt routine from accessing a hardware access by the task level.

The solution to the problem is to identify all of the write-only control registers that are shared between devices and tasks and to create a memory image block to keep a copy of the last thing written to the hardware. The address of this block is placed in a configuration table. The operating system/control program is given the responsibility to read a read-only memory (ROM) address for the input/output (I/O) attachment, obtain a memory block of the specified size, and set the address of the block in the correct configuration location. The ROM structure is modified to specify the number of bytes of common space required by the type of card. All tasks have access to the table to find the common write-only image memory block. Each task level routine is required to only access the block with interrupts blocked to avoid collision with the interrupt-processing routines. In addition, all software accesses work with the principle of 'ORing' in bits to set parameters and 'ANDing' to reset parameters in the block and then using the resulting value to update the hardware image.

To simplify the access of these registers and the software tracking of the values in them, a set of routines have been devised to manage the access. These are used by the tasks to avoid any mistakes in changing fields. One routine is provided to set bits according to a user-provided register selection code and a user-provided field of bit values. Another routine resets bits in the table with similar user input.

The use of write-only control registers is very common in single- device applications. When extended to multiple-device applications, the combination of control fields for each device in one register is generally avoided. In this situation, however, the limits on the design prevent the hardware from presenting a simpler interface to the software. This only requires the hardware to decode a write to the

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control address specified and requires no multiplexing for returning the control data on the path internally.

Sequences demonstrating the technique disclosed herein are set forth below. The sequence descriptions are preceded by the definitions of the terms used in the sequence descriptions.

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