Browse Prior Art Database

Process to Improve Sidewall Spacer Dimensional Control

IP.com Disclosure Number: IPCOM000036804D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Chesebro, DG: AUTHOR [+3]

Abstract

By adding a temporary layer over a silicon gate electrode, sidewall spacers are made to have more nearly vertical edge structure when anisotropic etching is used to expose the temporary layer. Thus horizontal dimensions of the spacers are more reliably equivalent to thickness of the spacer material. The temporary material is removed selectively before silicon is selectively grown on the exposed silicon gate electrode. This process results in a final gate electrode with its edges completely protected and contained by the sidewall spacer.

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Process to Improve Sidewall Spacer Dimensional Control

By adding a temporary layer over a silicon gate electrode, sidewall spacers are made to have more nearly vertical edge structure when anisotropic etching is used to expose the temporary layer. Thus horizontal dimensions of the spacers are more reliably equivalent to thickness of the spacer material. The temporary material is removed selectively before silicon is selectively grown on the exposed silicon gate electrode. This process results in a final gate electrode with its edges completely protected and contained by the sidewall spacer.

Referring to Fig. 1, a temporary layer 10 is deposited over gate electrode polysilicon layer 12 which is disposed over gate dielectric layer 14 on silicon substrate 16. Next, usual masking and etching is used to define lateral dimensions of polysilicon layer 12 and tempor ary overlayer 10. Sidewall spacer material 18 is then deposited conformally, as usual, to complete the cross section shown in Fig. 1.

Referring to Fig. 2, spacer material 18 is anisotropically etched to expose temporary layer 10. Note that overetching to assure exposing all of layer 10 everywhere on a large substrate is usual. Then, temporary layer 10 is selectively etched away to expose polysilicon gate 12. Next, selective silicon 20 is deposited as usual to complete the cross section shown in Fig. 2. Temporary layer 10 is made to be thicker than selective silicon 20 so that sidewall spacers 18 completely co...