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Clock Chopper in Cmos Gate Arrays

IP.com Disclosure Number: IPCOM000036814D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Le Garrec, JC: AUTHOR

Abstract

Designers need a variety of clock generation circuits depending on the type of clock distribution they are using.

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Clock Chopper in Cmos Gate Arrays

Designers need a variety of clock generation circuits depending on the type of clock distribution they are using.

A clock splitter circuit generates at a constant non-overlap time, and it is appropriate if it feeds a small number of Polarity Hold Shift Register Latches (PH SRLs). Skew in clock distribution makes this macro an unsafe design when driving large amount of logic because small separation of clocks requires analysis of minimum delays from latch to latch.

On the other hand, a clock chopper circuit provides clock separation which is controlled by the frequency of the input signal. An improved implementation of a clock chopper circuit is given hereafter. The operation principle may be understood from the logical representation and the circuit schematic, respectively, shown in Figs. 1 and 2.

The output pulse width is determined by the block 'DELAY' with devices 9 (P device) and i (N device). In the gate array environment, device 9 is defined with several P transistors in series with their gates connected to ground (Gnd). Device i is defined with several N transistors in series with their gates connected to a positive voltage (Vdd). Various output pulse widths can be provided by varying the delay path with the following configurations: Device 9 : 7, 13 or 19 P transistors in series

Device i : 7, 13 or 19 N transistors in series

B0 is an LSSD test clock which is pulled to a logical 1 during functional operation. Any defect in...