Browse Prior Art Database

Lssd-Testable 360-Degree Phase Detector

IP.com Disclosure Number: IPCOM000036818D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Galbraith, RL: AUTHOR [+2]

Abstract

Disclosed is a circuit for implementing a 360-degree phase detector which has LSSD test capability. LSSD (level sensitive scan design) is a widely accepted test methodology which provides an efficient and comprehensive means of testing clocked digital logic. The circuit provides the identical functions of the traditional 360-degree phase detector, yet has the advantage of being 100% testable using LSSD techniques, even though the circuit does not functionally operate as clocked logic. When this phase detector is included with other LSSD clocked logic, the composite circuitry can be tested using LSSD, and no functional test patterns need be implemented.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 4

Lssd-Testable 360-Degree Phase Detector

Disclosed is a circuit for implementing a 360-degree phase detector which has LSSD test capability. LSSD (level sensitive scan design) is a widely accepted test methodology which provides an efficient and comprehensive means of testing clocked digital logic. The circuit provides the identical functions of the traditional 360-degree phase detector, yet has the advantage of being 100% testable using LSSD techniques, even though the circuit does not functionally operate as clocked logic. When this phase detector is included with other LSSD clocked logic, the composite circuitry can be tested using LSSD, and no functional test patterns need be implemented.

The traditional 360-degree phase detector design is generally implemented using NOR logic gates and set-reset type latches. Fig. 1 illustrates this design. This implementation can be viewed as a free- running asynchronous state machine. The asynchronous set-reset-type latches provide the memory function for the state machine and are not

(Image Omitted)

clocked in any manner. The UP and DOWN (DN) outputs of the detector remain at logic low levels only when the rising edges of the SIG and REF inputs coincide. The UP output of the detector is pulsed to a logic high level when the frequency of the REF input is greater than that of the SIG input or when the phase of the REF input is considered to be leading that of the SIG input. The DN output of the detector is pulsed to a logic high level when the frequency of the SIG input is greater than that of the REF input or when the phase of the SIG input is considered to be leading that of the REF input.

Fig. 2 illustrates the flow table for this type of detector and shows three timing diagrams. The flow table indicates the status of the UP and DN outputs as the REF and SIG inputs are varied. The numbers in the table which are in parentheses are arbitrarily labeled to correspond to stable states. The numbers in the table which are not in parentheses refer to unstable states. Inp...