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Bandwidth Management of Statistical Time Division Multiplexing Via Buffer Queue Management

IP.com Disclosure Number: IPCOM000036833D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 107K

Publishing Venue

IBM

Related People

Petty, JC: AUTHOR [+2]

Abstract

This article describes a mechanism for efficient slot allocation on a synchronous time division multiplexed (STDM) bus as a function of the input demand for bandwidth.

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Bandwidth Management of Statistical Time Division Multiplexing Via Buffer Queue Management

This article describes a mechanism for efficient slot allocation on a synchronous time division multiplexed (STDM) bus as a function of the input demand for bandwidth.

The mechanism disclosed herein includes a statistical time division multiplex bus with multiple nodes vying for time slots, a bus

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arbiter with the task of allocating bus bandwidth and input nodes with buffer queues to hold incoming data until placed on the bus for delivery to other nodes. Fig. 1 is a diagrammatic illustration of a peer bus and arbitration bus.

A set of polling tag lines are provided between each node and the arbiter. Further, each node is connected to a four-bit bus for reporting buffer queue status to the arbiter each time it receives a poll tag signal from the arbiter. Each buffer queue has sufficient size to retain n slots worth of data and destination address. When reporting buffer queue status, the node encodes the buffer contents in terms of the equivalent number of slots it contains.

A frame on the STDM bus contains enough slots to empty some predetermined percentage of the total nodal buffer queue maximum capac

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ity. The arbiter assigns the slots for frames following the poll to each node in proportion to their demand. Each node in turn has separate input buffers for each port on the node and scans them in sequence and transfers their data in slot-size i...