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Elimination of Bus Contention During Chip-To-Chip Connectivity Test

IP.com Disclosure Number: IPCOM000036837D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Ratiu, IM: AUTHOR [+2]

Abstract

Disclosed is a method that eliminates bus contention during chip-to- chip DC connectivity testing for chips with boundary scan latches. The approach imposes a "one talker, many listeners" protocol by selectively disabling the primary outputs of the driving chips over a serial nonfunctional bus. First, the configuration of a chip with boundary scan latches and a model for the chip-to-chip wiring on a card are given, then the proposed solution preventing bus contention is explained.

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Elimination of Bus Contention During Chip-To-Chip Connectivity Test

Disclosed is a method that eliminates bus contention during chip-to- chip DC connectivity testing for chips with boundary scan latches. The approach imposes a "one talker, many listeners" protocol by selectively disabling the primary outputs of the driving chips over a serial nonfunctional bus. First, the configuration of a chip with boundary scan latches and a model for the chip-to- chip wiring on a card are given, then the proposed solution preventing bus contention is explained.

Fig. 1 shows the configuration of a chip with boundary scan latches. The boundary scan latches for the primary inputs are configured in a string with serial input SCANIN-1 and serial output SCANOUT-1; for the primary outputs, the serial input to the scan string is SCANIN-2 and the serial output is SCANOUT-2.

Signals entering the chip via the primary inputs may have to traverse some combinational logic to reach the input boundary scan latches. For signals sent out by the primary output boundary scan latches, the path may include some combinational logic, but must always include a tri-state driver. The output of this driver, the chip primary output pad, can be set in a high impedance state by activating control line HI-Z.

An example of a card with four chips, A through D, that contain boundary scan latches is presented in Fig. 2. The model assumes each

(Image Omitted)

chip connected to any other chip. For clarity, only a fraction of all possible connections are shown.

A non-functional serial bus supplies the decoded HI-Z control signals and chip address signals to all chips. Appropriate on-chip decoding logic allows the chip to act on or ignore t...