Browse Prior Art Database

Determination of Hardware Level With a Microcode Fragment

IP.com Disclosure Number: IPCOM000036847D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Schwartz, AA: AUTHOR [+2]

Abstract

A method is disclosed which permits discrimination between devices with identical function provided they both employ loadable microcode and there is a function which is microcoded in one, but not in the other.

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Determination of Hardware Level With a Microcode Fragment

A method is disclosed which permits discrimination between devices with identical function provided they both employ loadable microcode and there is a function which is microcoded in one, but not in the other.

The example described here is a floating point accelerator (FPA) which employs a microcoded control sequencer driven by a RAM control store which is loaded by the Loadable Power-On Self-Test (LPOST). The FPA exists in two versions, C and D. They are both microcoded, but they require slightly different microcode.

In order to differentiate between the two versions of the FPA, they had to be made to respond differently to an external stimulus. Among the differences between the C and D versions is the way the Write Float Register (WTFR) instruction is implemented. In the C version, WTFR is an ordinary instruction and is implemented in microcode. In the D version, it is implemented entirely in hardware with no involvement of the microcode.

The method of this invention is, prior to loading the normal microcode, to load a special microcode fragment which contains only a modified WTFR instruction, a Read Float Register (RDFR) instruction, and a minimum of initialzation microcode. Because this fragment is used under controlled conditions, no error handling microcode is required. The modified WTFR instruction consists of the normal WTFR followed by enough microcode to add the contents of the written register t...