Browse Prior Art Database

Extension of 8-Bit I/O Address Used to Load an 18-Bit Program Counter Register

IP.com Disclosure Number: IPCOM000036850D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Hill, KL: AUTHOR [+3]

Abstract

Anytime you need to load an I/O device that is more than 8-bits wide you are required to use more than one I/O address space on the system bus. Our objective was to load an 18-bit Program Counter register and only use one I/O address space instead of three. If we had used 3 I/O address spaces we could have easily loaded the Program Counter register and would have wasted six bits of the third I/O address space. The first two I/O address spaces would have been fully utilized. Each of the first two I/O address spaces would use all of their 8-bits of data to load the first 16-bits of the Program Counter register. But the third I/O address space would only need to use 2 of the 8 avail able data bits to finish loading the 18-bit Program Counter register.

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Extension of 8-Bit I/O Address Used to Load an 18-Bit Program Counter Register

Anytime you need to load an I/O device that is more than 8-bits wide you are required to use more than one I/O address space on the system bus. Our objective was to load an 18-bit Program Counter register and only use one I/O address space instead of three. If we had used 3 I/O address spaces we could have easily loaded the Program Counter register and would have wasted six bits of the third I/O address space. The first two I/O address spaces would have been fully utilized. Each of the first two I/O address spaces would use all of their 8-bits of data to load the first 16-bits of the Program Counter register. But the third I/O address space would only need to use 2 of the 8 avail able data bits to finish loading the 18-bit Program Counter register. By using our technique we only have the need for one I/O address space, which, in turn, avoids wasting six data bits of the third I/O address space. The circuit that allows us to do this is a small 2-bit counter which will be referred to as a Multi-Cycle Counter (MCC).

The write line for the Program Counter register is implemented in a PAL (programmable array logic) which decodes the I/O address and activates the write line by bringing it to a low state. Normally the PAL would decode three I/O addresses and would activate the write line to the Program Counter register three times so that it would be properly loaded. Instead two latches were...