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Enhanced Rotator Design for Aligning Store Data

IP.com Disclosure Number: IPCOM000036857D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Groves, RD: AUTHOR

Abstract

RISC processors, like the 801 and ROMP, have a 32-bit rotator as part of their execution unit. These processors must also support store instructions in which the bytes contained in the General-Purpose Register (GPR) being stored need to be rotated to align with the appropriate bytes on the memory/cache interface. This can be further complicated in a processor which supports misaligned operations, string instructions, and byte-reversed stores. By making a relatively minor modification to the rotator design and with an innovative rotator control circuit, the rotator can be shared for all of these functions with very little additional circuitry.

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Enhanced Rotator Design for Aligning Store Data

RISC processors, like the 801 and ROMP, have a 32-bit rotator as part of their execution unit. These processors must also support store instructions in which the bytes contained in the General-Purpose Register (GPR) being stored need to be rotated to align with the appropriate bytes on the memory/cache interface. This can be further complicated in a processor which supports misaligned operations, string instructions, and byte-reversed stores. By making a relatively minor modification to the rotator design and with an innovative rotator control circuit, the rotator can be shared for all of these functions with very little additional circuitry.

This description will be relative to a left rotator built out of cascaded multiplexers (muxes), but should be applicable to a wider class of designs. A well-known design technique for rotators is to cascade a series of multiplexers, each providing a different portion of the rotation. For example, in ROMP, the first 4-1 mux rotates either 0, 8, 16, or 24 bits left. This feeds a second mux which rotates left either 0, 2, 4, or 6 bits. The last 2-1 mux rotates 0 or 1 bits. By applying the proper control combination to these muxes, a rotate of from 0 to 31 bits can be performed (e.g., a rotate of 27 bits is performed by selecting 24 on the first mux, 2 on the second mux, and 1 on the last mux).

Two aspects of this design are to be noted. First, the order in which the muxes are cascaded is not important to the function, but may be important if the controls to some of the muxes are later than others. Second, note that the first level of mux is providing a byte shift capability. By simply separating the controls...