Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Highly Parallel Multi-Processor Initialization Process

IP.com Disclosure Number: IPCOM000036879D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Pfeiffer, RT: AUTHOR

Abstract

Disclosed is a concept which modifies the Initial Microcode Load sequence from a series of sequential steps into a highly parallel process. This concept implements a computer system of multiple processor units where each processor unit maintains both its program load and run-time parameters in a special non-volatile memory. The non-volatile memory allows each processor unit to function as an independent unit during system initialization.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

Highly Parallel Multi-Processor Initialization Process

Disclosed is a concept which modifies the Initial Microcode Load sequence from a series of sequential steps into a highly parallel process. This concept implements a computer system of multiple processor units where each processor unit maintains both its program load and run-time parameters in a special non- volatile memory. The non-volatile memory allows each processor unit to function as an independent unit during system initialization.

A computer system contains multi-processor units. Each processor unit has a local memory and is programmed to provide specific, limited functions, such as reading from or writing to storage media, communication lines, end-user workstations, and other functions. Current designs use dynamic random-access memories. This type of memory receives program loads during the initialization sequence following system power on and remains loaded while power is available. The concept, as disclosed, requires a special non-volatile memory technology in order to eliminate the need for program loads at initialization time.

It is possible to implement the concept using existing memory technologies, specifically dynamic random-access and electrically erasable programmable read-only memories. This approach has the problem that it requires two separately packaged memories. A memory technology exists, although not currently manufactured, which pairs a non-volatile memory cell with each dynamic ran...