Browse Prior Art Database

Decoder-Initiated Prefetching for LONG OP Instructions

IP.com Disclosure Number: IPCOM000036883D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

Several instructions in the 370 architecture have the capability to fetch from, or store into, multiple cache lines during a single execution of an instruction. For example: The STM instruction can store up to 64 bytes of information if all 16 registers are specified in the instruction's format. The MVC instruction can fetch and store up to 256 bytes of contiguous information. The MVCL instruction commonly is used to fetch and store several thousand bytes of contiguous information.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Decoder-Initiated Prefetching for LONG OP Instructions

Several instructions in the 370 architecture have the capability to fetch from, or store into, multiple cache lines during a single execution of an instruction. For example: The STM instruction can store up to 64 bytes of

information if all 16 registers are specified in the

instruction's format.

The MVC instruction can fetch and store up to 256 bytes

of contiguous information.

The MVCL instruction commonly is used to fetch and

store several thousand bytes of contiguous information.

During the execution of these instructions it is common to find that the operand information starts in one line of memory and then proceeds into an additional line of memory. If these additional lines of memory cause 'cache misses' these instructions must delay their execution while the requested line is brought into the cache. After the line is brought into the cache the instruction can continue its execution. The DECODER has the potential to eliminate the cache miss delay caused by referencing these additional lines of memory. The DECODER can recognize that the execution of one of these instructions will reference multiple lines of memory and initiate a prefetch to assure that the additional line of memory is in the cache even before the instruction begins its execution. For example, consider the execution of a STM instruction that will store all 16 registers. In this example 64 bytes of information must be stored. Assume that the operand save area is equally divided between two lines of memory. That is 32 bytes of the save area are in one line while the remaining 32 bytes of the save area are in the next line of memory. The DECODER can detect that the operand save area will extend into an additional line of memory and initiate a prefetch for that line even before the STM begins its execution. When the STM instruction is finally executed the second line can be already prefetched into the cache so that no execution delay is experienced.

Similarly, the EXECUTION unit can aid in reducing the cache miss delay caused by executing these instructions. The MVCL...