Browse Prior Art Database

Multiple Tier Software Timer

IP.com Disclosure Number: IPCOM000036894D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Dickinson, JL: AUTHOR [+2]

Abstract

A program is disclosed that detects short duration events very quickly when the missing event timeout time is relatively long.

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Multiple Tier Software Timer

A program is disclosed that detects short duration events very quickly when the missing event timeout time is relatively long.

A Multiple Tier Timer is useful when:

No hardware timers are available. Timing must be

done by microcode or programming.

Timed events do not cause interrupts

Events must be detected quickly to avoid impacting

performance. It is desirable to have as little

time as possible between the event and the code`s

detecting the event so that processing can

continue.

While the events normally occur very quickly

(within a few microseconds), they may take much

longer and are not errors until a much longer

period, even seconds have elapsed.

If the event is severely delayed, but still

completes within the permitted time, it is

permissible to have a longer delay detecting the

event.

In similar situations (assuming a byte-wide processor word), prior timers set up a counter several bytes wide to count the long timeout value. The program then looped checking for the event, incrementing the timer, and checking for a timeout. This includes considerable overhead to initialize the counter bytes, increment the low-order counter bytes, propagate the carry to the higher-order bytes and to check for the timeout - all in addition to checking for the desired event in the loop. If the event occurs shortly after checking for it, many instructions are executed to go through the loop again before again checking for the event. This causes a delay in detection and performance degradation.

In a Multiple Tier Timer, each tier is a separate conventional timer with a counter width wider than the previous tier. The following discussion describes a Multiple Tier Timer with three tiers, as shown in the figures.

The first tier has a counter width of zero, eliminating all counter initialization, incrementing, and counter testing. The first tier is simply a test for the event. If the event has occurred prior to executing the first tier, then there is no counter latency in detecting the event.

The first tier is a pretest. If it is anticipated that an event could typically occur immediately after this pretest, several pretest instructions could be strung out before the second tier at the expense of instruction storage.

If the event is not detected by the first tier, the second tier is entered. This is as tight a loop as possible. The second tier counter width is the smallest word that the processor can handle. Typically there is one instruction to initialize the counter and just 3 active instructions in the second tier loop:

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Test an...