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Address Adder With 100% Checking and Fast Parity Predict

IP.com Disclosure Number: IPCOM000036911D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 4 page(s) / 77K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

The figure shows the major elements of the address adder designed for 100% checking and a fast parity predict path. Complete checking means that every single stuck fault (stuck-at-0 and stuck-at-1) of an input and an output of a gate is detected. Each of two outputs of a gate may be in error independently.

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Address Adder With 100% Checking and Fast Parity Predict

The figure shows the major elements of the address adder designed for 100% checking and a fast parity predict path. Complete checking means that every single stuck fault (stuck-at-0 and stuck-at-1) of an input and an output of a gate is detected. Each of two outputs of a gate may be in error independently.

The address adder adds inputs B (B1,...,B31), X (X1,...,X31), and D (D20,...,D31) by means of a CSA (carry-save adder) and a PA (propa gate adder). The CSA produces carry outputs, Y (Y0,...,Y30) and sum outputs A (A1,...,A31). The Y and A outputs (except Y0) comprise the inputs to the PA, which produces the final sum outputs, S (S1,..., S31), and a carry that is ORed with Y0 to comprise the output carry, Cout.

The following error checks are included: 1. Alternate output carries, YA (Y0A,...,Y30A), from the CSA are generated for an XOR (exclusive OR) check of the PA. 2. Alternate functions of selected PA carries, CA, are generated for a carry look-ahead check. 3. Parity predict signals of S (PA sum) are produced and checked against parities generated from S. Byte parity is used.

The CSA produces sums (A) and carries (Y) as well as alternate carries (YA) according to the equations: Ai = BiOXi+Di Yi-1 = Yi-1A = Bi.Xi + Bi.Di + Xi.Di The equations are simplified for D=0.

The PA uses know CLA (carry look-ahead) methods to generate the final carries, from which the final sums (S) can be generated in an additional gating level. Final carries may be generated at non-contiguous bit positions, e.g., at even bit positions with two sum bits generated from each final carry.

Intermediate functions in the CLA typically include the single- bit functions: Gi = Ai.Yi

Pi = Ai+Yi

The single bit H functions, which are not needed in the CLA, are implemented as: Hi = Gi+Pi instead of the simpler Hi = Gi.Pi so as to force an error in H when P is stuck at 0 and G=1, or when G is stuck at 1 and P=0.

For an XOR check, the XOR parities are generated two ways and compared:

1. Input parities (PB, PX and PD - the 4-byte parities of B, X, and D, with suffixes 0 through 3) are XORed with the alternate set of output carries (YA) of the CSA. The XOR of the input parities represent the parities of A. Therefore, by byte XORs of YA with A represent the parities of the XOR of the PA inputs. The equation for the byte XOR, illustrated for byte 2, is: PXOR2 =

PA2+Y16AO...OY23A where PA2 = PB2OPX2OPD2

2. The byte XORs of the H signals are represented by the complement XOR of the H signals of the relevant byte. For byte 2 it is: H16O...OH23 The comparison produces an XOR error signal for each byte, which are ORed for a combined XOR ERROR signal. The equation

1

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for the byte 2 XOR error signal is: XOR ERROR (byte 2) =

PXOR2+H16+...+H23 Alternate PA carries are generated, each as a function of the preceding final carry and the intermediate P and G functions. For example, the alternate carry from bit 2 is: C...