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Bus-Locking Mechanism in an Intel 82385 Cache Controller Subsystem

IP.com Disclosure Number: IPCOM000036913D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Begun, RM: AUTHOR [+4]

Abstract

This article describes a lock circuit arrangement for use in an 82385 cache controller subsystem which increases cache efficiency.

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Bus-Locking Mechanism in an Intel 82385 Cache Controller Subsystem

This article describes a lock circuit arrangement for use in an 82385 cache controller subsystem which increases cache efficiency.

Fig. 1 is a block diagram of a personal computer system dual- bus/cache architecture. It includes a 25 MHz Intel 82385/80386 cache

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subsystem with 64K bytes of 30 ns static random-access memory (SRAM) for cache data. The 82385 cache controller provides bus isolation from the MICRO CHANNEL* bus for the 80386, as long as it remains executing out of its high speed cache. With a dual-bus/cache architecture there is much more bandwidth available to the 80386 on its private bus, and more for bus masters, intelligent I/O devices, etc., running concurrently on the MICRO CHANNEL bus. The 80386 accesses the MICRO CHANNEL bus through the 82385 cache controller, and the cycles that show up on the MICRO CHANNEL bus are I/O operations, buffered memory writes, the infrequent cache read misses, and all locked accesses.

The 82385 forces all locked 80386 cycles to run on the 82385 bus and the MICRO CHANNEL bus regardless of whether or not the referenced location resides in the cache. By implementing this "lock policy", many programs run much slower because the effective hit ratio of the cache is significantly less.

The purpose of the lock is to support a multi-processor environment, e.g., when it is critical that two or more bus cycles follow one another immediately. Otherwise, the cycles could be separated by a cycle from another bus master. The use of a test and set/exchange instruction for interprocessor semaphore communications is a good example of this condition. Suppose that the value of a semaphore register indicates the availability of a shared system device. If the 80386 reads the semaphore register to determine that the device is available, then writes a new value to the semaphore register to indicate that it intends to take control of...