Browse Prior Art Database

Diskette Verify Mode Operation Without DMA Controller Support

IP.com Disclosure Number: IPCOM000036919D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Wheeler, AR: AUTHOR

Abstract

This article describes a method and circuit implementation which improves personal computer system performance in multi-tasking environments by off-loading the "Verify Diskette" function from the direct memory access (DMA) controller.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 2

Diskette Verify Mode Operation Without DMA Controller Support

This article describes a method and circuit implementation which improves personal computer system performance in multi-tasking environments by off- loading the "Verify Diskette" function from the direct memory access (DMA) controller.

The diskette verification method currently in use relies on a

(Image Omitted)

special DMA controller mode which generates the normal DRQ/DACK handshake without asserting the corresponding CMD (IOR) signal. Diskette verify operations are thus similar to normal read operations, except that no data is transferred to the host system. Refer to Fig. 1 which shows the DMA read and verify timing. The actual verification performed is simply a cyclic redundancy check (CRC) of the data field, which is performed by the floppy disk controller (FDC). The FDC must receive appropriately timed DACK and TC pulses, however, in order to successfully perform the CRC check and terminate the command normally. Even though no data is transferred in this type of operation, the system bus remains unavailable during these "dummy" transfers.

The method disclosed herein adds a special mode to a first-in/ first-out (FIFO) data buffer located between the FDC and host system. This mode causes the FIFO control logic to generate the DACK, IOR, and TC signals necessary to perform the verify operation. No bus bandwidth or DMA resources are required for these local transfers, and the system is notified of the verification status upon command completion. Additiona...