Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Unchecked Logic Analyzer

IP.com Disclosure Number: IPCOM000036941D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Koo, CC: AUTHOR

Abstract

The program described is a quick way to find the upper bound of the Error Detection (ED) coverage for a Thermal Conduction Module (TCM) by analyzing the logic connections on a TCM. If the upper bound of the error detection coverage is low, then more checkers are needed in the design. The use of this program reduces processing time needed to discover the unconnected (unchecked) logic by orders of magnitude over such a state of the art technique as simulation.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 61% of the total text.

Page 1 of 2

Unchecked Logic Analyzer

The program described is a quick way to find the upper bound of the Error Detection (ED) coverage for a Thermal Conduction Module (TCM) by analyzing the logic connections on a TCM. If the upper bound of the error detection coverage is low, then more checkers are needed in the design. The use of this program reduces processing time needed to discover the unconnected (unchecked) logic by orders of magnitude over such a state of the art technique as simulation.

Traditionally, the error detection (ED) coverage is obtained by using fault simulation. A fault is injected into a logic network, then one uses simulation to see if the injected fault will cause any checker to be turned on. If any error checker comes on, then the injected fault is considered to be detectable by the checker. If none of the checkers is turned on, one cannot say that the fault is not detectable by any error checkers in the design. Hence, it is very difficult for anyone to calculate the ED coverage using fault simulation.

The un-checked logic analyzer (UCLA) program is a structure analyzer. It analyzes the connectivity of a logic network without studying the network functionality. If any logic block does not directly or indirectly connect to an error checker in a design, a fault at this block has no way to turn any error checker on via any method including fault simulation. Hence, UCLA is a quick way of finding the upper bound of the error detection coverage for a logic n...