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Four Device Complementary Metal Oxide Silicon Quasi Static Random Access Memory Cell

IP.com Disclosure Number: IPCOM000036967D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Davis, A: AUTHOR

Abstract

This four-device circuit has operational characteristics of a six- device static random-access memory (SRAM) cell when p-type device leakage exceeds subthreshold device current of its n-type devices. A refresh cycle or a word line driver circuit which does not pull the word line all the way up to supply voltage (Vdd) is required if p-type leakage is not excessive.

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Four Device Complementary Metal Oxide Silicon Quasi Static Random Access Memory Cell

This four-device circuit has operational characteristics of a six- device static random-access memory (SRAM) cell when p-type device leakage exceeds subthreshold device current of its n-type devices. A refresh cycle or a word line driver circuit which does not pull the word line all the way up to supply voltage (Vdd) is required if p-type leakage is not excessive.

Referring to the figure, p-type transistors T1 and T2 serve as pull-up devices. N-type transistors T3 and T4 serve as latch and pull-down devices. Transistors T3 and T4 are cross-coupled to form a latch, and their gate capacitance holds appropriate charge to maintain the stored data when the circuit is used as a true SRAM cell.

The cell is accessed through transistors T1 and T2. To write, a high level signal is applied to one of the bit lines BLL or BLR and a low level signal is applied to the other bit line. If bit line BLL is high and bit line BLR is low and word line WL is activated (pulled low), then transistor T1 conducts and transistor T2 does not conduct. Thus, node A is pulled high and node B is pulled low. This action takes place regardless of the previous voltage levels of nodes A and B.

When reading the cell, both bit lines BLL and BLR are floating at a high level because the bit lines are restored to a Vdd level. Word line WL is pulled low and, if node A is low, bit line BLL is pulled down by the series of t...