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Instruction Cache Bypass During Cache Reload Operation

IP.com Disclosure Number: IPCOM000036981D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Grohoski, GF: AUTHOR [+2]

Abstract

The time between the request for a cache line and the subsequent return of that cache line from memory is long enough in most cases to deplete the instructions available for dispatch to the execution units of a computer system. A further delay can be incurred if the instructions must be written to the cache and then fetched from the cache once the line has been completely transferred from main memory. A method will be described which tries to minimize the effects of this problem by bypassing instructions directly to the instruction unit as they return from memory.

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Instruction Cache Bypass During Cache Reload Operation

The time between the request for a cache line and the subsequent return of that cache line from memory is long enough in most cases to deplete the instructions available for dispatch to the execution units of a computer system. A further delay can be incurred if the instructions must be written to the cache and then fetched from the cache once the line has been completely transferred from main memory. A method will be described which tries to minimize the effects of this problem by bypassing instructions directly to the instruction unit as they return from memory.

The instruction fetch address register (IFAR) points to the next instruction to be fetched and therefore will reflect the address of a cache miss when one occurs. Once it has been determined that the miss request should be issued to memory, the IFAR is backed up into the instruction fetch address register shadow (IFARS) for later retrieval.

Instruction words are returned to the instruction cache in aligned pairs beginning with the pair containing the instruction that caused the cache miss. Pairs are returned sequentially up to the last pair of the cache line at which point a wrap occurs back to the first pair of instructions in that cache line and then continues until the entire line has been returned. The IFAR provides the address to the cache array indicating where to put the current instruction pair. As pairs are returned, the "word in cache line" portion of the IFAR is incremented by two in preparation for the next pair.

As instruction pairs are written into the cache, a "write- through" mode of cache array operation is used to provide these same two instructions to the instruction buffers. Thus instructions from...