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Browse Prior Art Database

Cost Reduction of a Processor Unit

IP.com Disclosure Number: IPCOM000036985D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Petz, BR: AUTHOR [+2]

Abstract

In certain computer systems, the primary CPU component is the PU (processor unit) chip. A specific challenge in the definition and design of the PU chips is the limitation presented with the number of input/ output pins (I/Os) allowed when using only one package. This VLSI (very large-scale integration) design presently utilizes a CMOS technology with a substrate having 231 I/Os. The following information describes a method by which the PU chip can further reduce its I/O count by 48 pins, thus allowing it to fit into a less expensive package.

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Cost Reduction of a Processor Unit

In certain computer systems, the primary CPU component is the PU (processor unit) chip. A specific challenge in the definition and design of the PU chips is the limitation presented with the number of input/ output pins (I/Os) allowed when using only one package. This VLSI (very large-scale integration) design presently utilizes a CMOS technology with a substrate having 231 I/Os. The following information describes a method by which the PU chip can further reduce its I/O count by 48 pins, thus allowing it to fit into a less expensive package. The features of this unit are: Multiplexing control store address bus with the BP

(base-pointer) bus

(Image Omitted)

Multiplexing control store data bus with

functional control lines while allowing no impact to

other processor chips

Meeting the required cycle time to support the low-end

performance

Savings per processor

Since the control store address lines from the processor unit are not used for the entire cycle on a RAM access, it is possible to multiplex other signals on these lines to other chips during the second half of the cycle.

Based on performance requirements for the systems, the cycle time for this processor is 120 NS. Using a four-phase clocking scheme, each clock has an active time of 30 NS and an inactive time of 90 NS. SRAM (static RAM) technology is used for the control store.

With the clocking structure used in the processor of the abovementioned certain computer, control signals are sampled once per cycle at the end of C1 time (Fig. 1)

As with most static RAMs, the address lines are not used the entire cycle. When addressing the control store, the address lines must be held constant 2 clock times. Since the address is only needed for this time, it can be taken away after C4 is active. This leaves almost half of the cycle available on the bus for other functional signals. Refer to Fig. 1 for these detailed timings. In Fig. 1, "Out Enbl" is output enable. The data coming out of the control store are enabled by the signals "Out Enbl".

Interfacing signals which are to be latched in other components at the end of C1 time are prime candidates for multiplexing on this bus. There are 13 address lines (see "Address" in Fig. 1), and the lines chosen for multiplexing on the bus are all storage control unit chip interface signals (BP/EAO/CEO/CSD in Fig. 1). Included will be the BP bus of 9 bits, the effective address overflow, t...