Browse Prior Art Database

Performance Monitoring of VLSI Devices

IP.com Disclosure Number: IPCOM000036991D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 5 page(s) / 55K

Publishing Venue

IBM

Related People

LeBlanc, JJ: AUTHOR [+4]

Abstract

Accurate performance assessment of a VLSI chip at the wafer level, while highly desirable, is an extremely difficult thing to do accurately. There are a number of reasons why this is a problem. First, in VLSI, the internal circuit elements are increasingly smaller and denser, while the off-chip drivers (OCDs) must maintain reasonable current-carrying capabilities. The switching of the OCDs during wafer test generates a significant di/dt. In CMOS, while the static current draw is small, significant current surges occur during the application of test patterns. The effect of these changes in current is enhanced by the unbypassed inductance of the chip/module tester and text fixture. If not controlled, the noise can cause power supply dips or ground bounce that will alter the state of internal latches.

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Performance Monitoring of VLSI Devices

Accurate performance assessment of a VLSI chip at the wafer level, while highly desirable, is an extremely difficult thing to do accurately. There are a number of reasons why this is a problem. First, in VLSI, the internal circuit elements are increasingly smaller and denser, while the off-chip drivers (OCDs) must maintain reasonable current-carrying capabilities. The switching of the OCDs during wafer test generates a significant di/dt. In CMOS, while the static current draw is small, significant current surges occur during the application of test patterns. The effect of these changes in current is enhanced by the unbypassed inductance of the chip/module tester and text fixture. If not controlled, the noise can cause power supply dips or ground bounce that will alter the state of internal latches. If during any portion of an applied pattern, the latches are disturbed, chances are very high that the test will fail. This alteration of states has the effect of causing a chip, which would operate faultlessly at higher package levels (in the system), to fail during chip/ module level testing. We would thus be scrapping good chips, at considerable cost. While the first problem is inductance related, the second problem is associated with the capacitive loading inherent in wafer testing. Optimal probe/tester interfaces in today's state-of- the-art testers provide capacitive loads of around 150 pf. VLSI chip drivers cannot drive such loads and still operate at 25 to 50 MHz.

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Similarly, synchronization of input signals at these higher speeds becomes next to impossible given the wafer test electrical environment. In the past, our inability to screen performance at the wafer level has caused us to defer such testing to higher levels of packaging. In this case, we risk the cost of packaging to whatever levels it takes to determine that the chip is truly too slow. While this cost may not be excessive when the package is a single chip module (SCM), it is an extremely expensive strategy when dealing with a multichip module (MCM). First, since a number of chips may be placed on the MCM, it may be difficult to accurately identify the truly defective chip. Secondly, MCMs are typically limited in how many times chips may be removed. If a MCM happened to be populated with a number of slow chips, or the entire supply of a particular chip was derived from a slow lot (quite possible), the entire MCM, with all its good chips and substrate would need to be scrapped, at a staggering cost. What is needed, therefore, is some way to assess the system performance of a chip when still in its wafer form. This assessment must be done in such a way that the "massive" inductance and capacitance inherent in wafer test does not adversely affect the results.

Solution: The solution is to deploy LSSD on-chip self-test (LOCST) in combination with specific tester waveforms to simulate the system environment and speed....