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IMPROVED CMOS DEVICE STRUCTURE AND FABRICATION PROCESS USING SELECTIVE DEPOSITION OF TiSi2

IP.com Disclosure Number: IPCOM000036996D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Harper, JME: AUTHOR [+4]

Abstract

The current technique for sub-micron CMOS fabrication (0.25 mm will be used as a reference) uses the deposition of 150 angstroms Ti on S/D regions, followed by a multi-step reaction/etch/anneal process to form self-aligned TiSi2 on S/D, about 300 angstroms thick. This process has limited success in smaller devices because of uneven formation of the silicide, instability at high temperature, consumption of doped Si leading to high contact resistance, and bridging to the gate. The high annealing temperature also degrades the dopant profile.

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IMPROVED CMOS DEVICE STRUCTURE AND FABRICATION PROCESS USING SELECTIVE DEPOSITION OF TiSi2

The current technique for sub-micron CMOS fabrication (0.25 mm will be used as a reference) uses the deposition of 150 angstroms Ti on S/D regions, followed by a multi-step reaction/etch/anneal process to form self-aligned TiSi2 on S/D, about 300 angstroms thick. This process has limited success in smaller devices because of uneven formation of the silicide, instability at high temperature, consumption of doped Si leading to high contact resistance, and bridging to the gate. The high annealing temperature also degrades the dopant profile.

Deposit TiSi2 as the source(S) and drain(D) contacts and on the gate poly-Si using the selective chemical vapor deposition (CVD) from a mixture of SiH4 and TiCl4 at a temperature of about 600oC [*]. The overall process sequence is shown in Fig. 1. The poly-Si thickness (Fig. 1a) can be less than 1000 angstroms since there is no consumption due to silicide deposition. Also, bridging is not expected to occur with selective CVD TiSi2, as it does in the salicide process, so less poly-Si is needed for purely topographic reasons. The screen oxide (Fig. 1c) for implantation of S/D (Fig. 1d) can also be used as a spacer (Fig. 1e) in the selective deposition of TiSi2 (Fig. 1f), allowing the fabrication of smaller structures. The resistivity of such selective CVD TiSi2 is 15-25 mL-cm, indicating that the film is in the C54 crystal structure as deposited. The usual salicide process requires an anneal at 800oC to convert the C49 (high resistivity) phase to the low resistivity C54 phase. Therefore, the use of the selective silicide removes requirement for an annealing treatment above 600oC.

Since the deposition is selective on Si and poly-Si, there is no growth on the surrounding oxide surface, providing a self-aligned process without any etching step to remove unreacted material, and without bridging. However, also because of the selectivity, the cleaning of the contact areas is important. Th...