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Memory Error Isolation for Manufacturing

IP.com Disclosure Number: IPCOM000036997D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Grosbach, LE: AUTHOR [+2]

Abstract

The figure illustrates a technique for isolating failing memory modules in a working system. As part of the manufacturing process, processors are tested, and although memory errors usually won't stop the processor, it is desirable to fix any memory errors when found. Isolating memory modules permits Manufacturing the ability to replace defective main storage modules by using only the processor itself and not an additional card tester. It is not always possible to use a card tester on the memory cards.

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Memory Error Isolation for Manufacturing

The figure illustrates a technique for isolating failing memory modules in a working system. As part of the manufacturing process, processors are tested, and although memory errors usually won't stop the processor, it is desirable to fix any memory errors when found. Isolating memory modules permits Manufacturing the ability to replace defective main storage modules by using only the processor itself and not an additional card tester. It is not always possible to use a card tester on the memory cards.

During initial program load, tests are run on the AS/400 hardware, and if a memory error is detected while fetching data, the processor is stopped. The corrected data from the fetch are obtained from the hardware register that was the destination of the fetch. If the error is uncorrectable, then the destination register is not loaded. In order to locate the failing memory modules, one needs to know the address of the main storage error and the data fetched from it. To do this, the memory controller is set up to save the main storage address where the error occurred. Now, by looking at a new register that was added to the main storage data correction logic, one can see the original data fetched from the main storage. This allows a bit-by-bit comparison of the fetched data versus the corrected data to determine which bits in main storage are bad, as shown in the figure. Using this information with the main storage address saved...