Browse Prior Art Database

Screen-Mode Decoder

IP.com Disclosure Number: IPCOM000036998D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Kobayashi, M: AUTHOR [+2]

Abstract

Disclosed is a screen-mode decoder circuit for a multi-mode display monitor which has the capability to display at least four different modes of screen.

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Screen-Mode Decoder

Disclosed is a screen-mode decoder circuit for a multi-mode display monitor which has the capability to display at least four different modes of screen.

Most of the current display monitors, especially in PC (Personal Computer) use, are required to display more than two different screen modes, such as 640 dots by 400 dots and 1024 dots by 768 dots. In order to identify the screen- mode status from a controller to a display monitor, polarity changing, according to the screen-mode status, of horizontal and vertical sync signals is widely used.

The disclosed circuit, an interface circuit of a display monitor for the above application, consists of two integral circuits, a quadruple packed Exclusive-OR gate IC, a pair of diodes, a resistor and an inverter device such as a transistor.

(Image Omitted)

Fig. 1 is a diagram of the decoder circuit, and Fig. 2 shows a truth table of the terminals indicated in Fig. 1. The decoder circuit receives horizontal and vertical sync signals whose polarity is positive and/or negative from a controller. The decoder provides the positive TTL level horizontal and vertical sync signals with a monitor circuit because a constant polarity signal is required in the monitor circuit. In addition, the decoder circuit outputs a total of three lines of mode status signals to a display monitor circuit. These lines are indicated as HSL-1, HSL-2 and HSL-3 in Figs. 1 and 2. In default mode, that is, both horizontal sync and vertica...