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Reordering Buffered Requests for Improved Performance

IP.com Disclosure Number: IPCOM000037021D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Hardell, WR: AUTHOR [+4]

Abstract

Disclosed is a means to increase performance by reordering buffere requests. In this implementation the request buffering logic will present its highest priority request for servicing. The buffering logic must know when the presented request is being serviced. If the presented request is not being serviced, it can be swapped for another request. The swapping occurs when a higher priority request than the presented request is received by the buffering logic. Reordering of buffered requests can continue until the presented request starts being processed. The buffering logic must know the last cycle that a request is needed. The cycle after the last cycle that a request is needed, the buffering logic will present a new request (if there is a buffered request waiting servicing).

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Reordering Buffered Requests for Improved Performance

Disclosed is a means to increase performance by reordering buffere requests. In this implementation the request buffering logic will present its highest priority request for servicing. The buffering logic must know when the presented request is being serviced. If the presented request is not being serviced, it can be swapped for another request. The swapping occurs when a higher priority request than the presented request is received by the buffering logic. Reordering of buffered requests can continue until the presented request starts being processed. The buffering logic must know the last cycle that a request is needed. The cycle after the last cycle that a request is needed, the buffering logic will present a new request (if there is a buffered request waiting servicing).

For example, consider a system with a Storage Control Unit (SCU) that receives memory requests from a Processor Bus (P-Bus). The requests are Store-Backs, D-Cache Reloads, and I-Cache Reloads. Also, there are scrub and DMA requests for memory. It may take 6 or more cycles from the time a memory operation starts until it finishes. Figure 1 shows the handshaking between the P- Bus buffering and the memory control logic. The P-bus buffering logic generates three request signals, one for each of the following: Store-Backs, D-Cache Reloads, and I-Cache Reloads. The memory control logic generates a signal indicating that it is using the presented P-Bus request and that request cannot be changed. The memory control logic, also, generates a signal indicating the last cycle that a request is needed.

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Fig. 2 shows a simple example of the timing diag...