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Package Level Programmable Chip Architecture

IP.com Disclosure Number: IPCOM000037037D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+2]

Abstract

Steering circuits are included on dynamic random-access memory (DRAM) chips which may be programmed by appropriate connection to one or more program pads at the time of packaging to select a desired architecture. Thus, chips with identical construction may be configured to meet different architectural requirements late in the manufacturing cycle and fewer part numbers exist in the manufacturing line.

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Package Level Programmable Chip Architecture

Steering circuits are included on dynamic random-access memory (DRAM) chips which may be programmed by appropriate connection to one or more program pads at the time of packaging to select a desired architecture. Thus, chips with identical construction may be configured to meet different architectural requirements late in the manufacturing cycle and fewer part numbers exist in the manufacturing line.

One example of programmable chip architecture is that of a million-bit DRAM chip basically configured as a 256Kx4 DRAM chip without read-modify-write (RMF) having a single programmable input pad to change chip architecture to a 1Mbx1 with RMF. Referring to the figure, which is a data flow diagram, a single program pad PGM on the chip is connected to high supply voltage Vdd by any of several means to cause the chip to operate in the 1Mbx1 with RMF mode. When pad PGM is at ground potential, the chip is programmed to operate in the 256Kx4 mode. Chip pads must also be wired as shown in the following pin assignment table for x1 or x4 operation. Number of Number Connected For

Chip Pads x1 x4

Vdd 1 1 1

Ground 1 1 1

Vsx (Subst. Voltage) 1 - -

DQ (Data In/Out) 4 1 4

D (Data In) 1 1 -

RE (Row Energize) 1 1 1

CE (Column Energize) 1 1 1

G (Output Enable) 1 - 1

WE (Write Enable) 1 1 1

PGM (Program) 1 - -

ADD (Address) 10 10 9

Total 23 17 19

Referring again to the figure, having pad PGM at voltage Vdd, the 1 of 4 decode circuit 12 is set by input signals on lines ADD, RE, and CE such that one of the four steering circuits 14, 16, 18 and 20, also receiving a Vdd input, is set to accept the next input of data D through receiver 22 and send it to data latches DL1, DL2, DL3 and DL4 associated with memory array quadrants Q1, Q2, Q3, and Q4. Data out is always steered through off-chip driver 24 to pad DQ1, regardless of the quadr...