Browse Prior Art Database

Frame Handler With Dynamic Allocation of Buffer Space

IP.com Disclosure Number: IPCOM000037041D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 3 page(s) / 77K

Publishing Venue

IBM

Related People

Birman, A: AUTHOR [+3]

Abstract

Disclosed is a design of a frame handler with dynamic allocation of buffer space. The design, which can be implemented in hardware with standard components, enables efficient utilization of buffer space and allows the high speed and flexible operation of this packet-switching system.

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Frame Handler With Dynamic Allocation of Buffer Space

Disclosed is a design of a frame handler with dynamic allocation of buffer space. The design, which can be implemented in hardware with standard components, enables efficient utilization of buffer space and allows the high speed and flexible operation of this packet-switching system.

The frame handler consists of three components: an N-to-1 switch, a frame processor and a 1-to-N switch. Both the N-to-1 switch and the 1-to-N switch require buffers for storing packets and thus can benefit from the use of dynamic allocation of buffer space (the 1-to-N switch is used in the illustrations below). The "N" side of these switches attaches to a TDM link. The TDM slots are arbitrarily allocated to the N channels.

(Image Omitted)

Figs. 1 and 2 illustrate the structure of the 1-to-N switch (SEL denotes a data selector, and MUX denotes a data multiplexer). The inputs to the system are: Data/pkt, an 8-bit data bus carrying bytes of incoming packets; Cha#/pkt, an address bus carrying the output channel number which is the destination of the incoming packet; and Clock, an external clock for both the input channel and the TDM output link. The output of the system consists of an 8-bit data bus, Data/slot, representing the TDM output link.

The Slot Counter is a counter which takes the external clock as input and outputs the TDM Slot Number. The Slot/Channel Map is a storage unit which maps TDM slot numbers into channel numbers.

Data Buffers is a storage unit which stores bytes of data packets from the time of their arrival at the system over the input channel, until their departure from the system over their intended destination, one of the N output channels. This storage unit is partitioned in equal-size contiguous areas called buffers. The buffers are dynam ically allocated to one of N buffer chains corresponding to the N output channels. A buffer is allocated to a buffer chain by removing it from the pool of free buffers and by appending it at the end of the buffer chain.

Similarly, a buffer is deallocated from a buffer chain by removing it from the beginning of the chain and by returning it to the pool of free buffers.

In a buffer chain, bytes of data are stored contiguously, their location is identified by two pointers: a read pointer (R-ptr) pointing to the next data byte to be read, and a write pointer (W-ptr) pointing to the location where the next arriving byte is to be written. An incoming byte is stored in the location pointed to by the write pointer, while the outgoing byte is read from the location pointed to by the read pointer.

The Write Pointer Table (W-table) and the Read Pointer Table (R-table) are storage units which store the two pointers for every buffer chain. Since there is a buffer chain for every output channel, the number of entries in these units equals the maximum number of output channels. W-ptr/pckt is a register associated with the writing of packets to Data Buffers...