Browse Prior Art Database

Very Fast Single-Cycle Wire-And for Multi-Point Nets

IP.com Disclosure Number: IPCOM000037058D
Original Publication Date: 1989-Nov-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Hardell, WR: AUTHOR [+3]

Abstract

Disclosed is a means to wire-AND a multi-point net which cannot be practically pulled up in one processor cycle. This implementation uses a pair of signals with alternate active and dead cycles.

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Very Fast Single-Cycle Wire-And for Multi-Point Nets

Disclosed is a means to wire-AND a multi-point net which cannot be practically pulled up in one processor cycle. This implementation uses a pair of signals with alternate active and dead cycles.

To achieve a combination of pin minimization and pulling the signal up in a single cycle, two alternating signals are used. The cycle after a particular signal is driven low, the chip that detected the error (and drove the signal low) drives the signal high inactive. The chip that receives the signals will AND the two signals together to create one signal that represents the AND of all the outputs.

(Image Omitted)

In the multi-point dotted net shown in Figure 1, a typical wire-AND function is implemented. All the drivers are Open-Collector type-drivers. Any one of the chips can drive the signal low. All of the chip drivers must be at a high impedance state for the signal to be in a high state.

In most systems the signal must be at a known state at every clock edge. If the clock period is small then the resistor value must be very small to pull the line up to a high state quickly. However, if the resistor is very small, the drivers may not be able to drive the signals low in one cycle. Additionally, a resistor with a very small value will waste a large amount of power.

In this method, two wire-ANDed signals are used on alternating cycles (see Figure 2). Each chip must know which signal to use on which cycle. The chips ca...